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intelligent power module and gate drive interface optocouplers technical data features ? performance specified for common ipm applications over industrial temperature range: -40 c to 100 c ? fast maximum propagation delays t phl = 480 ns t plh = 550 ns ? minimized pulse width distortion pwd = 450 ns ? 15 kv/ m s minimum common mode transient immunity at v cm = 1500 v ? ctr > 44% at i f = 10 ma ? safety approval ul recognized -2500 v rms / 1 min. for hcpl-4506/0466 -3750 v rms / 1 min. for hcpl-j456 -5000 v rms / 1 min. for hcpl-4506 option 020 and hcnw4506 csa approved bsi certified (hcnw4506) vde0884 approved -v iorm = 560 vpeak for hcpl-0466 option 060 -v iorm = 630 vpeak for hcpl-4506 option 060 -v iorm = 891 vpeak for hcpl-j456 -v iorm = 1414 vpeak for hcnw4506 the connection of a 0.1 m f bypass capacitor between pins 5 and 8 is recommended. applications ? ipm isolation ? isolated igbt/mosfet gate drive ? ac and brushless dc motor drives ? industrial inverters hcpl-4506 hcpl-j456 hcpl-0466 hcnw4506 caution: it is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by esd. functional diagram truth table led v o on l off h 8 7 6 1 3 shield 5 2 4 20 k w nc anode cathode nc v cc v l v o gnd
2 selection guide standard white mold package 8-pin dip 8-pin dip small outline widebody type (300 mil) (300 mil) so8 (400 mil) hermetic* part hcpl-4506 hcpl-j456 hcpl-0466 hcnw4506 hcpl-5300 number hcpl-5301 vde0884 v iorm = 630 vpeak v iorm = 891 vpeak v iorm = 560 vpeak v iorm = 1414 vpeak approval (option 060) (option 060) *technical data for these products are on separate agilent publications. ordering information specify part number followed by option number (if desired). example: hcpl-4506#xxx 020 = ul 5000 v rms/1 minute option** for hcpl-4506 only. 060 = vde0884 option** for hcpl-4506/0466. 300 = gull wing lead option for hcpl-4506/j456, hcnw4506. 500 = tape and reel packaging option option data sheets are available. contact agilent sales representative or authorized distributor for information. **combination of option 020 and option 060 is not available. description the hcpl-4506 and hcpl-0466 contain a gaasp led while the hcpl-j456 and the hcnw4506 contain an algaas led. the led is optically coupled to an inte- grated high gain photo detector. minimized propagation delay difference between devices makes these optocouplers excellent solutions for improving inverter efficiency through reduced switching dead time. an on chip 20 k w output pull-up resistor can be enabled by shorting output pins 6 and 7, thus eliminating the need for an external pull-up resistor in common ipm applications. specifications and performance plots are given for typical ipm applications.
3 package outline drawings hcpl-4506 and hcpl-j456 outline drawing 0.635 ?0.25 (0.025 ?0.010) 12?nom. 9.65 ?0.25 (0.380 ?0.010) 0.635 ?0.130 (0.025 ?0.005) 7.62 ?0.25 (0.300 ?0.010) 5 6 7 8 4 3 2 1 9.65 ?0.25 (0.380 ?0.010) 6.350 ?0.25 (0.250 ?0.010) 1.016 (0.040) 1.194 (0.047) 1.194 (0.047) 1.778 (0.070) 9.398 (0.370) 9.906 (0.390) 4.826 (0.190) typ. 0.381 (0.015) 0.635 (0.025) pad location (for reference only) 1.080 ?0.320 (0.043 ?0.013) 4.19 (0.165) max. 1.780 (0.070) max. 1.19 (0.047) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) hcpl-4506 and hcpl-j456 gull wing surface mount option 300 outline drawing 9.65 ?0.25 (0.380 ?0.010) 1.78 (0.070) max. 1.19 (0.047) max. a xxxxz yyww date code 1.080 ?0.320 (0.043 ?0.013) 2.54 ?0.25 (0.100 ?0.010) 0.51 (0.020) min. 0.65 (0.025) max. 4.70 (0.185) max. 2.92 (0.115) min. dimensions in millimeters and (inches). 5 6 7 8 4 3 2 1 5?typ. option code* ul recognition ur 0.254 + 0.076 - 0.051 (0.010 + 0.003) - 0.002) 7.62 ?0.25 (0.300 ?0.010) 6.35 ?0.25 (0.250 ?0.010) type number * marking code letter for option numbers (hcpl-4506). "l" = option 020 "v" = option 060 option numbers 300 and 500 not marked.
4 hcpl-0466 outline drawing (8-pin small outline package) hcnw4506 outline drawing (8-pin widebody package) xxx yww 8765 4 3 2 1 5.994 ?0.203 (0.236 ?0.008) 3.937 ?0.127 (0.155 ?0.005) 0.406 ?0.076 (0.016 ?0.003) 1.270 (0.050) bsg 5.080 ?0.127 (0.200 ?0.005) 3.175 ?0.127 (0.125 ?0.005) 1.524 (0.060) 45?x 0.432 (0.017) 0.228 ?0.025 (0.009 ?0.001) type number (last 3 digits) date code 0.305 (0.012) min. total package length (inclusive of mold flash) 5.207 ?0.254 (0.205 ?0.010) dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches) max. 0.203 ?0.102 (0.008 ?0.004) 7 pin one 0 ~ 7 * * 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 1.78 ?0.15 (0.070 ?0.006) 5.10 (0.201) max. 1.55 (0.061) max. 2.54 (0.100) typ. dimensions in millimeters (inches). 7?typ. 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) 11.00 (0.433) 9.00 ?0.15 (0.354 ?0.006) max. 10.16 (0.400) typ. a hcnwxxxx yyww date code type number 0.51 (0.021) min. 0.40 (0.016) 0.56 (0.022) 3.10 (0.122) 3.90 (0.154)
5 note: use of nonchlorine activated fluxes is recommended. solder reflow temperature profile 1.00 ?0.15 (0.039 ?0.006) 7?nom. 12.30 ?0.30 (0.484 ?0.012) 0.75 ?0.25 (0.030 ?0.010) 11.00 (0.433) 5 6 7 8 4 3 2 1 11.15 ?0.15 (0.442 ?0.006) 9.00 ?0.15 (0.354 ?0.006) 1.3 (0.051) 12.30 ?0.30 (0.484 ?0.012) 6.15 (0.242) typ. 0.9 (0.035) pad location (for reference only) 1.78 ?0.15 (0.070 ?0.006) 4.00 (0.158) max. 1.55 (0.061) max. 2.54 (0.100) bsc dimensions in millimeters (inches). lead coplanarity = 0.10 mm (0.004 inches). 0.254 + 0.076 - 0.0051 (0.010 + 0.003) - 0.002) max. 240 d t = 115?, 0.3?/sec 0 d t = 100?, 1.5?/sec d t = 145?, 1?/sec time ?minutes temperature ?? 220 200 180 160 140 120 100 80 60 40 20 0 260 123 456789101112 hcnw4506 gull wing surface mount option 300 outline drawing
6 insulation and safety related specifications value parameter symbol hcpl-4506 hcpl-j456 hcpl-0466 hcnw4506 units conditions minimum external l(101) 7.1 7.4 4.9 9.6 mm measured from input air gap (external terminals to output clearance) terminals, shortest distance through air. minimum external l(102) 7.4 8.0 4.8 10.0 mm measured from input tracking (external terminals to output creepage) terminals, shortest distance path along body. minimum internal 0.08 0.5 0.08 1.0 mm through insulation plastic gap distance, conductor to (internal clearance) conductor, usually the direct distance between the photoemitter and photodetector inside the optocoupler cavity. minimum internal na na na 4.0 mm measured from input tracking (internal terminals to output creepage) terminals, along internal cavity. tracking resistance cti 3 175 3 175 3 175 3 200 volts din iec 112/vde 0303 (comparative part 1 tracing index) isolation group iiia iiia iiia iiia material group (din vde 0110, 1/89, table 1) regulatory information the devices contained in this data sheet have been approved by the following agencies: agency/standard hcpl-4506 hcpl-j456 hcpl-0466 hcnw4506 underwriters laboratories (ul) ul 1577 recognized under ul 1577, component 4444 recognized program, category fpqu2, file e55361 canadian standards component association (csa) acceptance 4444 file ca88324 notice #5 verband deutscher din vde 0884 electrotechniker (vde) (june 1992) 44 4 technischer din vde 0884 uberwachungs-verein (june 1992) rheinland (tuv) certificate r9650938 4 british certification according to standards bs en60065: 1994(bs415:1994), institute bs en 60950: 1992(bs7002:1992), 4 (bsi) and iec 65(1985). all agilent data sheets report the creepage and clearance inherent to the optocoupler component itself. these dimensions are needed as a starting point for the equipment designer when determining the circuit insulation require- ments. however, once mounted on a printed circuit board, minimum creepage and clearance requirements must be met as specified for individual equipment standards. for creepage, the shortest distance path along the surface of a printed circuit board between the solder fillets of the input and output leads must be considered. there are recom- mended techniques such as grooves and ribs which may be used on a printed circuit board to achieve desired creepage and clearances. creepage and clearance distances will also change depending on factors such as pollution degree and insulation level.
7 vde 0884 insulation related characteristics hcpl-0466 hcpl-4506 description symbol option 060 option 060 hcpl-j456 hcnw4506 unit installation classification per din vde 0110/1.89, table 1 for rated mains voltage 150 v rms i-iv i-iv i-iv i-iv for rated mains voltage 300 v rms i-iii i-iv i-iv i-iv for rated mains voltage 450 v rms i-iii i-iii i-iv for rated mains voltage 600 v rms i-iii i-iv for rated mains voltage 1000 v rms i-iii climatic classification 55/100/21 55/100/21 55/100/21 55/100/21 pollution degree 2 2 2 2 (din vde 0110/1.89) maximum working v iorm 560 630 891 1414 v peak insulation voltage input to output test voltage, method b* v iorm x 1.875 = v pr , 100% production test with t m =v pr 1050 1181 1670 2652 v peak 1 sec, partial discharge < 5pc input to output test voltage, method a* v iorm x 1.5 = v pr , type and sample test, t m = 60 sec, v pr 840 945 1336 2121 v peak partial discharge < 5pc highest allowable overvoltage* v iotm 4000 6000 6000 8000 v peak (transient overvoltage, t ini = 10 sec) safety limiting values C maximum values allowed in the event of a fail- ure, also see thermal derating curve. case temperature t s 150 175 175 150 c input current i s input 150 230 400 400 ma output power p s output 600 600 600 700 mw insulation resistance at t s ,r s 3 10 9 3 10 9 3 10 9 3 10 9 w v io = 500 v *refer to the optocoupler section of the designer's catalog, under regulatory information (vde 0884) for a detailed description of method a and method b partial discharge test profiles. note: these optocouplers are suitable for "safe electrical isolation" only within the safety limit data. maintenance of the safety data shall be ensured by means of protective circuits. note: insulation characteristics are per din vde 0884 (june 1992 revision). note: surface mount classification is class a in accordance with cecc 00802.
8 absolute maximum ratings parameter symbol min. max. units storage temperature t s -55 125 c operating temperature t a -40 100 c average input current [1] i f(avg) 25 ma peak input current [2] (50% duty cycle, 1 ms pulse width) i f(peak) 50 ma peak transient input current (<1 m s pulse width, 300 pps) i f(tran) 1.0 a reverse input voltage (pin 3-2) hcpl-4506, hcpl-0466 v r 5 volts hcpl-j456, hcnw4506 3 average output current (pin 6) i o(avg) 15 ma resistor voltage (pin 7) v 7 -0.5 v cc volts output voltage (pin 6-5) v o -0.5 30 volts supply voltage (pin 8-5) v cc -0.5 30 volts output power dissipation [3] p o 100 mw total power dissipation [4] p t 145 mw lead solder temperature (hcpl-4506, hcpl-j456) 260 c for 10 s, 1.6 mm below seating plane lead solder temperature (hcnw4506) 260 c for 10 s (up to seating plane) infrared and vapor phase reflow temperature see package outline drawings section (hcpl-0466 and option 300) recommended operating conditions parameter symbol min. max. units power supply voltage v cc 4.5 30 volts output voltage v o 0 30 volts input current (on) i f(on) 10 20 ma input voltage (off) v f(off) * -5 0.8 v operating temperature t a -40 100 c *recommended v f(off) = -3 v to 0.8 v for hcpl-j456, hcnw4506.
9 electrical specifications over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol device min. typ.* max. units test conditions fig. note current transfer ratio ctr 44 90 % i f = 10 ma, 5 v o = 0.6 v low level output current i ol 4.4 9.0 ma i f = 10 ma, 1, 2 v o = 0.6 v low level output voltage v ol 0.3 0.6 v i o = 2.4 ma input threshold current i th hcpl-4506 1.5 5 ma v o = 0.8 v, 1 16 hcpl-0466 i o = 0.75 ma hcnw4506 hcpl-j456 0.6 high level output current i oh 550 m av f = 0.8 v 3 high level supply current i cch 0.6 1.3 ma v f = 0.8 v, 16 v o = open low level supply current i ccl 0.6 1.3 ma i f = 10 ma, 16 v o = open input forward voltage v f hcpl-4506 1.5 1.8 v i f = 10 ma 4 hcpl-0466 hcpl-j456 1.2 1.6 1.95 5 hcnw4506 1.6 1.85 temperature coefficient d v f / d t a hcpl-4506 -1.6 mv/ ci f = 10 ma of forward voltage hcpl-0466 hcpl-j456 hcnw4506 -1.3 input reverse breakdown bv r hcpl-4506 5 v i r = 10 m a voltage hcpl-0466 hcpl-j456 3 i r = 100 m a hcnw4506 input capacitance c in hcpl-4506 60 pf f = 1 mhz, hcpl-0466 v f = 0 v hcpl-j456 72 hcnw4506 internal pull-up resistor r l 14 20 25 k w t a = 25 c12, 13 internal pull-up resistor d r l / d t a 0.014 k w / c temperature coefficient *all typical values at 25 c, v cc = 15 v. ?v f(off) = -3 v to 0.8 v for hcpl-j456, hcnw4506.
10 switching specifications (r l = 20 k w external) over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol min. typ.* max. units test conditions fig. note propagation delay t phl 30 200 400 ns c l = 100 pf i f(on) = 10 ma, 6, 8, 11, time to logic hcpl-j456 480 v f(off) = 0.8 v, 10- 14, low at output 100 c l = 10 pf v cc = 15.0 v, 13 16 propagation delay t plh 270 400 550 ns c l = 100 pf v thlh = 2.0 v, time to high v thhl = 1.5 v output level 130 c l = 10 pf pulse width pwd 200 450 ns c l = 100 pf 20 distortion propagation delay t plh -t phl -150 200 450 ns 17 difference between any 2 parts output high level |cm h | 15 30 kv/ m si f = 0 ma, v cc = 15.0 v, 7 18 common mode v o > 3.0 v c l = 100 pf, transient immunity v cm = 1500 v p-p output low level |cm l | 15 30 kv/ m si f = 10 ma t a = 25 c19 common mode v o < 1.0 v transient immunity switching specifications (r l = internal pull-up) over recommended operating conditions unless otherwise specified: t a = -40 c to +100 c, v cc = +4.5 v to 30 v, i f(on) = 10 ma to 20 ma, v f(off) = -5 v to 0.8 v? parameter symbol min. typ.* max. units test conditions fig. note propagation delay t phl 20 200 400 ns i f(on) = 10 ma, v f(off) = 0.8 v, 6, 9 11-14, time to logic hcpl-j456 485 v cc = 15.0 v, c l = 100 pf, 16 low at output v thlh = 2.0 v, v thhl = 1.5 v propagation delay time t plh 220 450 650 ns to high output level pulse width pwd 250 500 ns 20 distortion propagation delay t plh -t phl -150 250 500 ns 17 difference between any 2 parts output high level |cm h | 30 kv/ m si f = 0 ma, v cc = 15.0 v, 7 18 common mode v o > 3.0 v c l = 100 pf, transient immunity v cm = 1500 v p-p , output low level |cm l | 30 kv/ m si f = 16 ma, t a = 25 c19 common mode v o < 1.0 v transient immunity power supply psr 1.0 v p-p square wave, t rise , t fall 16 rejection > 5 ns, no bypass capacitors *all typical values at 25 c, v cc = 15 v. ?v f(off) = -3 v to 0.8 v for hcpl-j456, hcnw4506.
11 package characteristics over recommended temperature (t a = -40 c to 100 c) unless otherwise specified. parameter sym. device min. typ.* max. units test conditions fig. note input-output momentary v iso hcpl-4506 2500 v rms rh < 50% 6,7,10 withstand voltage? hcpl-0466 t = 1 min. hcpl-j456 3750 t a = 25 c 6,8,10 hcpl-4506 5000 6,9, option020 15 hcnw4506 5000 6,9,10 resistance r i-o hcpl-4506 10 12 v i-o = 500 vdc 6 (input-output) hcpl-j456 w hcpl-0466 hcnw4506 10 12 10 13 capacitance c i-o hcpl-4506 0.6 pf f = 1 mhz 6 (input-output) hcpl-0466 hcpl-j456 0.8 hcnw4506 0.5 notes: 1. derate linearly above 90 c free-air temperature at a rate of 0.8 ma/ c. 2. derate linearly above 90 c free-air temperature at a rate of 1.6 ma/ c. 3. derate linearly above 90 c free-air temperature at a rate of 3.0 mw/ c. 4. derate linearly above 90 c free-air temperature at a rate of 4.2 mw/ c. 5. current transfer ratio in percent is defined as the ratio of output collector current (i o ) to the forward led input current (i f ) times 100. 6. device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together. 7. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 3000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 8. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 4500 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 9. in accordance with ul 1577, each optocoupler is proof tested by applying an insulation test voltage 3 6000 v rms for 1 second (leakage detection current limit, i i-o 5 m a). 10. this test is performed before the 100% production test shown in the vde 0884 insulation related characteristics table, if applicable. 11. pulse: f = 20 khz, duty cycle = 10%. 12. the internal 20 k w resistor can be used by shorting pins 6 and 7 together. 13. due to tolerance of the internal resistor, and since propagation delay is dependent on the load resistor value, performance can be improved by using an external 20 k w 1% load resistor. for more information on how propagation delay varies with load resistance, see figure 8. 14. the r l = 20 k w , c l = 100 pf load represents a typical ipm (intelligent power module) load. 15. see option 020 data sheet for more information. 16. use of a 0.1 m f bypass capacitor connected between pins 5 and 8 can improve performance by filtering power supply line noise. 17. the difference between t plh and t phl between any two devices under the same test condition. (see ipm dead time and propagation delay specifications section.) 18. common mode transient immunity in a logic high level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic high state (i.e., v o > 3.0 v). 19. common mode transient immunity in a logic low level is the maximum tolerable dv cm /dt of the common mode pulse, v cm , to assure that the output will remain in a logic low state (i.e., v o < 1.0 v). 20. pulse width distortion (pwd) is defined as |t phl - t plh | for any given device. * all typical values at 25 c, v cc = 15 v. ?the input-output momentary withstand voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous voltage rating. for the continuous voltage rating refer to the vde 0884 insulation related characteristics table (if applicable), your equipment level safety specification or agilent application note 1074 entitled optocoupler input-output endurance voltage, publication number 5963-2203e.
12 figure 4. hcpl-4506 and hcpl-0466 input current vs. forward voltage. figure 5. hcpl-j456 and hcnw4506 input current vs. forward voltage. figure 2. normalized output current vs. temperature. figure 1. typical transfer characteristics. figure 3. high level output current vs. temperature. figure 6. propagation delay test circuit. i o ?output current ?ma 0 i f ?forward led current ?ma 6 4 2 5 10 10 15 20 v o = 0.6 v 8 0 100 ? 25 ? -40 ? normalized output current t a ?temperature ?? 0.95 0.90 0.85 0 40 60 100 i f = 10 ma v o = 0.6 v 1.00 -40 -20 20 80 1.05 0.80 i oh ?high level output current ?? t a ?temperature ?? 15.0 10.0 5.0 0 40 60 100 20.0 -40 -20 20 80 0 4.5 v 30 v v f = 0.8 v v cc = v o = 4.5 v or 30 v i f ?forward current ?ma 1.10 0.001 v f ?forward voltage ?volts 1.60 10 1.0 0.1 1.20 1000 1.30 1.40 1.50 t a = 25? i f v f + 0.01 100 hcpl-4506/0466 i f ?input forward current ?ma 0.001 v f ?input forward voltage ?v 1 0.1 0.01 1.0 100 1.4 1.8 2.0 t a = 25 ? 10 0.8 1.2 1.6 i f v f + hcpl-j456/hcnw4506 0.1 ? v cc = 15 v 20 k w i f(on) =10 ma v out c l * + *total load capacitance + i f v o v thhl t phl t plh t f t r 90% 10% 90% 10% v thlh 8 7 6 1 3 shield 5 2 4 5 v 20 k w
13 t p ?propagation delay ?ns rl ?load resistance ?k w 600 400 200 30 50 800 010 20 40 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf t a = 25 ? figure 8. propagation delay with external 20 k w rl vs. temperature. figure 9. propagation delay with internal 20 k w rl vs. temperature. figure 10. propagation delay vs. load resistance. figure 7. cmr test circuit. typical cmr waveform. figure 13. propagation delay vs. input current. figure 11. propagation delay vs. load capacitance. figure 12. propagation delay vs. supply voltage. 0.1 ? v cc = 15 v 20 k w a i f v out 100 pf* + *100 pf total capacitance + + b v ff v cm = 1500 v 8 7 6 1 3 shield 5 2 4 20 k w v cm d t ov v o v o switch at a: i f = 0 ma switch at b: i f = 10 ma v cc v ol v cm d t d v d t = t p ?propagation delay ?ns t a ?temperature ?? 400 300 200 0 40 60 100 500 -40 -20 20 80 t plh t phl i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k w (external) 100 t p ?propagation delay ?ns 0 cl ?load capacitance ?pf 800 600 400 100 1400 200 300 400 i f = 10 ma v cc = 15 v rl = 20 k w t a = 25? 200 1000 t plh t phl 1200 0 500 t p ?propagation delay ?ns 0 v cc ?supply voltage ?v 800 600 400 10 1400 15 20 25 i f = 10 ma cl = 100 pf rl = 20 k w t a = 25? 200 1000 t plh t phl 530 1200 t p ?propagation delay ?ns 100 i f ?forward led current ?ma 300 10 500 15 v cc = 15 v cl = 100 pf rl = 20 k w t a = 25? 200 400 t plh t phl 5 020 t p ?propagation delay ?ns t a ?temperature ?? 400 300 200 0 40 60 100 600 -40 -20 20 80 t plh t phl 100 i f = 10 ma v cc = 15 v cl = 100 pf rl = 20 k w (internal) 500
14 figure 16. optocoupler input to output capacitance model for unshielded optocouplers. figure 15. recommended led drive circuit. figure 14. thermal derating curve, dependence of safety limiting value with case temperature per vde 0884. figure 18. led drive circuit with resistor connected to led anode (not recommended). figure 17. optocoupler input to output capacitance model for shielded optocouplers. 0.1 ? v cc = 15 v 20 k w cmos 310 w +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k w 8 7 6 1 3 shield 5 2 4 c ledp c ledn 20 k w 8 7 6 1 3 shield 5 2 4 c ledp c ledn c led01 c led02 20 k w 0.1 ? v cc = 15 v 20 k w cmos 310 w +5 v v out 100 pf + *100 pf total capacitance 8 7 6 1 3 shield 5 2 4 20 k w output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 p s (mw) hcpl-4506 option 060/hcpl-j456 175 (230) i s (ma) for hcpl-4506 option 060 i s (ma) for hcpl-j456 output power ?p s , input current ?i s 0 0 t s ?case temperature ?? 175 1000 50 400 125 25 75 100 150 600 800 200 100 300 500 700 900 p s (mw) for hcnw4506 i s (ma) for hcnw4506 hcpl-0466 option 060/hcnw4506 p s (mw) for hcpl-0466 option 060 i s (ma) for hcpl-0466 option 060 (150)
15 figure 23. recommended led drive circuit for ultra high cmr. figure 20. ac equivalent circuit for figure 15 during common mode transients. figure 19. ac equivalent circuit for figure 18 during common mode transients. figure 21. not recommended open collector led drive circuit. figure 22. ac equivalent circuit for figure 21 during common mode transients. q1 +5 v 8 7 6 1 3 shield 5 2 4 20 k w 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledp c ledn c led01 c led02 i cledn* q1 +5 v 8 7 6 1 3 shield 5 2 4 20 k w 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. 310 w v out 100 pf + i total* v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledn c led01 c led02 i cledp i f c ledp i cled01 20 k w * the arrows indicate the direction of current flow for +dv cm /dt transients. ** optional clamping diode for improved cmh performance. v r < v f (off) during +dv cm /dt. v out 100 pf + v cm 8 7 6 1 3 shield 5 2 4 20 k w c ledp c ledn c led01 c led02 i cledn* 310 w + v r **
16 figure 24. typical application circuit. figure 26. waveforms for dead time calculation. figure 25. minimum led skew for zero dead time. 0.1 ? 20 k w cmos 310 w +5 v v out1 i led1 v cc1 m hcpl-4506 hcpl-4506 hcpl-4506 hcpl-4506 hcpl-4506 q2 q1 -hv +hv ipm 8 7 6 1 3 shield 5 2 4 20 k w hcpl-4506 0.1 ? 20 k w cmos 310 w +5 v v out2 i led2 v cc2 8 7 6 1 3 shield 5 2 4 20 k w hcpl-4506 v out1 v out2 i led2 t plh max. pdd* max. = (t plh- t phl ) max. = t plh max. - t phl min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference note: the propagation delays used to calculate pdd are taken at equal temperatures. v out1 v out2 i led2 t plh min. maximum dead time (due to optocoupler) = (t plh max. - t plh min. ) + (t phl max. - t phl min. ) = (t plh max. - t phl min. ) - (t plh min. - t phl max. ) = pdd* max. - pdd* min. t phl min. i led1 q1 on q2 off q1 off q2 on *pdd = propagation delay difference t plh max. t phl max. pdd* max. max. dead time note: the propagation delays used to calculate the maximum dead time are taken at equal temperatures.
17 led drive circuit considerations for ultra high cmr performance without a detector shield, the dominant cause of optocoupler cmr failure is capacitive coupl- ing from the input side of the optocoupler, through the package, to the detector ic as shown in figure 16. the hcpl-4506 series improve cmr performance by using a detector ic with an optically transparent faraday shield, which diverts the capacitively coupled current away from the sensitive ic circuitry. however, this shield does not eliminate the capacitive coupling between the led and the optocoupler output pins and output ground as shown in figure 17. this capacitive coupling causes perturbations in the led current during common mode transients and becomes the major source of cmr failures for a shielded opto coupler. the main design objective of a high cmr led drive circuit becomes keeping the led in the proper state (on or off) during common mode transients. for example, the recommended application circuit (figure 15), can achieve 15 kv/ m s cmr while minimizing component complexity. note that a cmos gate is recommended in figure 15 to keep the led off when the gate is in the high state. another cause of cmr failure for a shielded optocoupler is direct coupling to the optocoupler output pins through c ledo1 and c ledo2 in figure 17. many factors influence the effect and magni- tude of the direct coupling including: the use of an internal or external output pull-up resistor, the position of the led current setting resistor, the connection of the unused input package pins, and the value of the capacitor at the optocoupler output (c l ). techniques to keep the led in the proper state and minimize the effect of the direct coupling are discussed in the next two sections. cmr with the led on (cmr l ) a high cmr led drive circuit must keep the led on during common mode transients. this is achieved by overdriving the led current beyond the input threshold so that it is not pulled below the threshold during a transient. the recommended minimum led current of 10 ma provides adequate margin over the maximum i th of 5.0 ma (see figure 1) to achieve 15 kv/ m s cmr. capacitive coupling is higher when the internal load resistor is used (due to c ledo2 ) and an i f = 16 ma is required to obtain 10 kv/ m s cmr. the placement of the led current setting resistor effects the ability of the drive circuit to keep the led on during transients and interacts with the direct coupling to the optocoupler output. for example, the led resistor in figure 18 is connected to the anode. figure 19 shows the ac equivalent circuit for figure 18 during common mode transients. during a +dvcm/dt in figure 19, the current available at the led anode (itotal) is limited by the series resistor. the led current (i f ) is reduced from its dc value by an amount equal to the current that flows through c ledp and c ledo1 . the situation is made worse because the current through c ledo1 has the effect of trying to pull the output high (toward a cmr failure) at the same time the led current is being reduced. for this reason, the recommended led drive circuit (figure 15) places the current setting resistor in series with the led cathode. figure 20 is the ac equivalent circuit for figure 15 during common mode transients. in this case, the led current is not reduced during a +dvcm/dt transient because the current flowing through the package capacitance is supplied by the power supply. during a -dvcm/dt transient, however, the led current is reduced by the amount of current flowing through c ledn . but, better cmr performance is achieved since the current flowing in c ledo1 during a negative transient acts to keep the output low. coupling to the led and output pins is also affected by the con- nection of pins 1 and 4. if cmr is limited by perturbations in the led on current, as it is for the recommended drive circuit (figure 15), pins 1 and 4 should be connected to the input circuit common. however, if cmr performance is limited by direct coupling to the output when the led is off, pins 1 and 4 should be left unconnected. cmr with the led off (cmr h ) a high cmr led drive circuit must keep the led off (v f v f(off) ) during common mode transients. for example, during a +dvcm/dt transient in figure 20, the current flowing through c ledn is supplied by the parallel combination of the led and series resistor. as long as the voltage developed across the resistor is less than v f(off) the
18 led will remain off and no common mode failure will occur. even if the led momentarily turns on, the 100 pf capacitor from pins 6-5 will keep the output from dipping below the threshold. the recommended led drive circuit (figure 15) provides about 10 v of margin between the lowest optocoupler output voltage and a 3 v ipm threshold during a 15 kv/ m s transient with v cm = 1500 v. additional margin can be obtained by adding a diode in parallel with the resistor, as shown by the dashed line con- nection in figure 20, to clamp the voltage across the led below v f(off) . since the open collector drive circuit, shown in figure 21, cannot keep the led off during a +dvcm/dt transient, it is not desirable for applications requiring ultra high cmr h performance. figure 22 is the ac equivalent circuit for figure 21 during common mode transients. essentially all the current flowing through c ledn during a +dvcm/dt transient must be supplied by the led. cmr h failures can occur at dv/dt rates where the current through the led and c ledn exceeds the input threshold. figure 23 is an alternative drive circuit which does achieve ultra high cmr performance by shunting the led in the off state. ipm dead time and propagation delay specifications the hcpl-4506 series include a propagation delay difference specification intended to help designers minimize dead time in their power inverter designs. dead time is the time period during which both the high and low side power transistors (q1 and q2 in figure 24) are off. any overlap in q1 and q2 conduction will result in large currents flow- ing through the power devices between the high and low voltage motor rails. to minimize dead time the designer must consider the propa- gation delay characteristics of the optocoupler as well as the charac- teristics of the ipm igbt gate drive circuit. considering only the delay characteristics of the opto- coupler (the characteristics of the ipm igbt gate drive circuit can be analyzed in the same way) it is important to know the minimum and maximum turn-on (t phl ) and turn-off (t plh ) propagation delay specifications, preferably over the desired operating temperature range. the limiting case of zero dead time occurs when the input to q1 turns off at the same time that the input to q2 turns on. this case determines the minimum delay between led1 turn-off and led2 turn-on, which is related to the worst case optocoupler propaga- tion delay waveforms, as shown in figure 25. a minimum dead time of zero is achieved in figure 25 when the signal to turn on led2 is delayed by (t plh max - t phl min ) from the led1 turn off. note that the propagation delays used to calculate pdd are taken at equal temperatures since the opto- couplers under consideration are typically mounted in close proximity to each other. (specifically, t plh max and t phl min in the previous equation are not the same as the t plh max and t phl min , over the full operating temperature range, specified in the data sheet.) this delay is the maximum value for the propaga- tion delay difference specification which is specified at 450 ns for the hcpl-4506 series over an operating temperature range of -40 c to 100 c. delaying the led signal by the maximum propagation delay dif- ference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. the maximum dead time occurs in the highly unlikely case where one opto- coupler with the fastest t plh and another with the slowest t phl are in the same inverter leg. the maximum dead time in this case becomes the sum of the spread in the t plh and t phl propagation delays as shown in figure 26. the maximum dead time is also equivalent to the difference between the maximum and mini- mum propagation delay difference specifications. the maximum dead time (due to the optocoup- lers) for the hcpl-4506 series is 600 ns (= 450 ns - (-150 ns) ) over an operating temperature range of -40 c to 100 c.
19
www.semiconductor.agilent.com data subject to change. copyright ? 1999 agilent technologies obsoletes 5965-6168e 5968-1089e (11/99)

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